1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method of forming a dual damascene pattern.
2. Description of the Related Art
According to Moore's law, the integration degree of a semiconductor device may increase two times every year. Such an increase of the integration degree in semiconductor chips leads to micro-sized transistors and interconnections.
As the interconnections are fabricated in a micro-size, resistance R and capacitance C between interconnections are increased, so that the RC delay time is lengthened. Such an increase of the RC delay time causes degradation of the response speed and performance of the semiconductor device.
Recently, metal interconnections are fabricated by using copper having resistance lower than that of aluminum in order to reduce parasitic capacitance between metal interconnections. In addition, instead of an interlayer dielectric layer including silicon oxide (SiO2, k≈4.2), an interlayer dielectric layer including one or more low-k materials, such as FSG (fluorinated silicate glass, k≈3.7) or OSG (organosilicate glass, k≈2.8) may be used so as to reduce parasitic capacitance between metal interconnections.
Different from an aluminum interconnection process, a copper interconnection is fabricated through a dual damascene process. According to the dual damascene process, a low-k insulating layer formed at an interconnection area is removed through an etching process by using a PR (photoresist) mask, and then a metallic interconnection material (Cu) is filled therein.
According to the dual damascene process, via holes and trenches are formed in the low-k insulating layer, and then a PR film used for forming the via holes and/or trenches is removed in order to form the metal interconnections. The PR removal process aims not only to remove the PR film, but also to reduce damage of the interlayer dielectric layer and to minimize polymer residues remaining in the via holes and/or trenches while preventing an oxide layer from being formed on the copper interconnection. In particular, when the PR removal process is performed at a high temperature, the interlayer dielectric layer may be damaged or the oxide layer may be formed on the copper interconnection. For this reason, the PR removal process is generally performed at a low temperature (e.g., 20to 25° C.) when the copper interconnection process is carried out. After the PR removal process, particles may be introduced onto a wafer. In this case, the characteristics of the semiconductor device may be degraded. In addition, since the PR removal process takes a relatively long time as compared to the via bole/trench forming process, the overall process time is lengthened.
Hereinafter, a conventional dual damascene process will be described with reference to accompanying drawings.
FIGS. 1A to 1C are sectional view showing the conventional dual damascene process, and FIG. 2 is a view showing an SEM image of particles, which are generated when a conventional asher apparatus is used.
Referring to FIG. 1A, a first etch stop layer 2, a first interlayer dielectric layer 3, a second etch stop layer 4, a second interlayer dielectric layer 5, and a cap insulating layer 6 are sequentially formed on a substrate 1.
The first etch stop layer 2 includes a nitride layer used as a barrier layer, and the second interlayer dielectric layer 5 includes FSG (fluorinated silicate glass) or OSG (organosilicate glass).
After sequentially forming the above layers 2 to 6 on the substrate 1, a first PR film is coated on the cap insulating layer 6. Then, the PR film is selectively patterned, thereby forming a first PR pattern for exposing a part of the cap insulating layer 6.
Then, the cap insulating layer 6, the second interlayer dielectric layer 5, the second etch stop layer 4 and the first interlayer dielectric layer 3 are sequentially etched by using the first PR pattern as a mask, thereby forming a via hole having a first width such that the first etch stop layer 2 can be exposed through the via hole.
After that, the first PR film, which is aligned on the cap insulating layer 6 to form the via hole, is removed. Then, a bottom antireflection coating (BARC) layer is formed in the via hole and a planarization process is performed such that the BARC layer remains only in the via hole, thereby forming a sacrificial layer 7 in the via hole.
Subsequently, after forming a BARC layer 8 on the entire surface of the resultant structure, a second PR film 9 is formed on the BARC layer 8. Then, the second PR film 9 is patterned such that a part of the BARC layer 8 can be exposed.
After that, as shown in FIG. 1B, the BARC layer 8, the cap insulating layer 6 and the second interlayer dielectric layer 5 are patterned by using the second PR film 9 as an etch mask, thereby forming a trench 10 extending through the BARC layer 8, the cap insulating layer 6 and the second interlayer dielectric layer 5. At this time, a polymer layer 11, which is a byproduct created during the trench forming process, can be formed on the surfaces of the trench 10 and the second PR film 9.
Referring to FIG. 1C, after the trench 10 has been formed, the substrate 1 is loaded into an usher apparatus so as to remove the second PR film 9, the polymer layer 11, the BARC layer 8, and the sacrificial layer 7 from the substrate 1. Accordingly, the second PR film 9, the polymer layer 11, the BARC layer 8, and the sacrificial layer 7 are sequentially removed from the substrate 1 in the usher apparatus, so that the via hole 14 and the french 10 are formed.
As mentioned above, according to the conventional damascene process, the trench forming process for forming the trench in the layers provided on the substrate 1 is performed separately from the asher process for removing the PR film.
The asher apparatus for performing the ashing process removes the PR film through a downstream scheme by using a microwave (2.45 GHz) or an ICP (inductively coupled plasma) source.
Such an asher apparatus generally uses a waveguide and an RF antenna, and also uses a chamber having an increased volume in order to realize the downstream scheme in the chamber, so particles may be generated in the chamber. In addition, since the trench forming process and the PR removal process are performed in different chambers, the manufacturing steps may be relatively high.
The conventional asher apparatus performs the ashing process through two steps or one step. In particular, if the ashing process is performed through two steps, the second PR film is partially removed during the first step by generating plasma using a bias power, and then the remaining part of the second PR film and the sacrificial layer are removed during the second step by using the microwave downstream.
However, in order to remove the second PR film and the sacrificial layer by using the microwave downstream, the chamber of the asher apparatus must have a large volume, which may cause particles in the chamber.
For instance, if the ashing process is performed by using the asher apparatus having a large-sized chamber, as shown in FIG. 2 illustrating SEM (scanning electron microscope) images of devices processed in such a chamber, a plurality of particles may be generated in the chamber. The particles may cause a short circuit in the copper layer when the copper layer is subjected to a chemical mechanical polishing (CMP) process.
In addition, in order to form the trench after forming the via hole, the conventional dual damascene process patterns the PR film or the sacrificial layer including the BARC layer after filling the via hole with the PR film or the sacrificial layer. In this case, however, the sacrificial layer is not always completely removed from the via hole, so that residues of the sacrificial layer may remain in the via hole.